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Circuit techniques for 1.5-V CMOS DRAMS to be used in battery-based applications are presented. A three-level word pulse and a plate pulse are used to maintain the stored voltage in a memory cell, in spite of the minimized data-line voltage swing for reducing power dissipation. A 3.4- mu m2 data-line shielded stacked capacitor (STC) cell is also proposed to enhance signal-to-noise ratio (SNR) in the memory cell array. The 1.5-V read/write operation is observed successfully through a 2-kbit test device. The data-holding time and alpha -particle-induced soft error rate of the device indicate that the possible performances for the 1.5-V DRAM are comparable to those for the existing 5-V DRAMs.