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A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

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9 Author(s)
K. Arimoto ; LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Itami, Japan ; K. Fujishima ; Y. Matsuda ; M. Tsukude
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A single 3.3-V 16-Mbit DRAM with a 135-mm2 chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-line (TBL) array, includes suitable dummy and space word-line configurations which suppress the inter-bit-line noise and bring yield improvement. The multipurpose register (MPR) designed for the hierarchical data bus structure provides a line-mode test (LMT), copy write, and cache access capability. The LMT with on-chip test circuits using the MPR and a comparator creates a random test pattern and reduces the test time to 1/1000. A field shield isolation and a T-shaped stacked capacitor allow the layout of a 4.8- mu m2 cell size with a storage capacitance of 35 fF. These techniques enable the 3.3-V 16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power dissipation at 120-ns cycle time.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 5 )