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A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance

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5 Author(s)
S. Chou ; Oki Electr. Ind. Co. Ltd., Tokyo, Japan ; T. Takano ; A. Kita ; F. Ichikawa
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Discusses three new techniques that were implemented in a CMOS 60-ns 16-Mbit DRAM device. (1) A two-step half-conductive-state technique was used to control the conductivity of latch transistors, thus minimizing the time delay caused by bit-line stray capacitance. (2) The 'split-block row decoder' technique enabled the decoder layout within the 2.9- mu m cell pitch required for 16-Mbit integration density. The three transistors that are required per word line were split into two and one, placed on both sides of each word line, and alternately reversed on each side of the 2-Mbit cell array. (3) Additional dummy cells were added to the vacant spaces resulting from use of a twisted bit-line architecture, which reduces stray capacitance between adjacent bit lines. The overhead space required for all the dummy cells and twisted bit lines was thus held at 2.6 percent of the entire chip area.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 5 )