Skip to Main Content
A digitally controlled frequency-doubling phase-shifter architecture is presented for the implementation of multiple-antenna GHz transceiver systems. It takes a 1.75 GHz input and produces two phase-shifted outputs at 3.5 GHz. It consists of a Delay Locked Loop (DLL) followed by symmetric XOR frequency doublers and phase interpolators. The phase shifter prototype in 90 nm standard CMOS has a phase shift range of 360° with a resolution of 22.5° and an INL <; 12° (<; 4° with external adjust), and consumes 55 mW from a 1 V supply.