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Symmetric Varactor in 130-nm CMOS for Frequency Multiplier Applications

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2 Author(s)
Dongha Shim ; Electr. & Comput. Eng. Dept., Univ. of Florida, Gainesville, FL, USA ; Kenneth, K.O.

A symmetric varactor (SVAR) in 130-nm digital complementary metal-oxide-semiconductor (CMOS) for frequency multiplier applications with the maximum cutoff frequency of ~320 GHz and a dynamic cutoff frequency of ~125 GHz is demonstrated. To demonstrate the generation of odd-order harmonics and suppression of even-order ones, an SVAR was measured at the pumping frequency of 900 MHz. The measured third-order harmonic power is more than 25 dB higher than that for the second order. Harmonic balance simulations showed that the SVAR pumped by a 50-GHz signal source can generate a 150-GHz third-harmonic output signal with 15.8-dB minimum conversion loss at the input power of 7.8 dBm. The SVAR can be integrated with other (CMOS) components to generate millimeter-wave signals.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 4 )

Date of Publication:

April 2011

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