By Topic

Impact of static and dynamic stress on threshold voltage instability in high-k/metal gate n-channel metal-oxide-semiconductor field-effect transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

13 Author(s)
Dai, Chih-Hao ; Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan ; Chang, Ting-Chang ; Chu, Ann-Kuo ; Kuo, Yuan-Jui
more authors

Your organization might have access to this article on the publisher's site. To check, click on this link: 

This letter investigates the impact of static and dynamic stress on threshold voltage (Vth) instability in ultrathin n-channel metal-oxide-semiconductor field-effect transistors with hafnium-based gate stacks. Experimental results indicate Vth shift under dynamic stress is more serious than that under static stress due to charge trapping within the high-k dielectric. Capacitance-voltage techniques demonstrated that electron trapping under dynamic stress was located in the high-k dielectric near the source/drain overlap region rather than throughout the overall dielectric layer. This implies in real circuit operation, the phenomenon of electrons trapped in high-k near the source/drain overlap is the main issue affecting Vth instability.

Published in:

Applied Physics Letters  (Volume:98 ,  Issue: 9 )