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This paper focuses on synchronization of radio frequency identification (RFID) reader receivers, which plays a significant role for stability and efficiency of RFID systems. Performance of RFID reader suffers from a back-link-frequency variation of tags at a maximum of 22% according to widely used RFID standards. A new synchronization scheme employing timing recovery loop in RFID Reader Receivers is presented to solve the problem with less hardware cost. Simulation results give an improved performance compared with conventional schemes. The design is implemented on Xilinx Spartan-3E FPGA and function is verified on our RFID test platform.