Analysis of parasitic effects of small-outline packages for high-frequency integrated circuits

This study reports the packaging effects of a small-outline package (SOP) on overall electrical characteristics of RFICs. The parameters of an equivalent coupled-π model circuit are extracted from simulated S-parameters at low frequency. These parameters are then optimized over the desired frequency range for better accuracy. To verify the obtained circuit model, the tuning characteristic of a voltage controlled oscillator (VCO) was tested. The circuit is fabricated using a 0.5 um N-well CMOS process, and packaged in a 28-lead SOP plastic package. Experimental results are shown to closely match the simulation results.