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Analysis of parasitic effects of small-outline packages for high-frequency integrated circuits

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2 Author(s)
Chen Zhai ; Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA ; Dawood, M.

This study reports the packaging effects of a small-outline package (SOP) on overall electrical characteristics of RFICs. The parameters of an equivalent coupled-π model circuit are extracted from simulated S-parameters at low frequency. These parameters are then optimized over the desired frequency range for better accuracy. To verify the obtained circuit model, the tuning characteristic of a voltage controlled oscillator (VCO) was tested. The circuit is fabricated using a 0.5 um N-well CMOS process, and packaged in a 28-lead SOP plastic package. Experimental results are shown to closely match the simulation results.

Published in:

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Date of Conference:

12-15 Dec. 2010