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Low power sensor node processor architecture

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4 Author(s)
Panic, G. ; Frankfurt Oder, IHP, Frankfurt (Oder), Germany ; Basmer, T. ; Tittelbach-Helmrich, K. ; Lopacinski, L.

This paper presents a low power solution for sensor node processor architecture, where an asynchronous processor has been integrated with a number of peripherals in a quite unique fashion. The paper describes the most important architectural and design issues and presents the implementation results.

Published in:

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Date of Conference:

12-15 Dec. 2010