By Topic

Column parallel single-slope ADC with time to digital converter for CMOS imager

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Muung Shin ; Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan ; Ikebe, M. ; Motohisa, J. ; Sano, E.

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. Single-slope ADCs have been used as column parallel ADCs for CMOS image sensors. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability. We designed a 12-bit ADC, which consists of the 3-bit TDC and the 9-bit-single-slope ADC, by using a 0.25-μm CMOS process. Through SPICE simulation, we confirmed our single-slop ADC to be more consistent, have more robust meta-stability, and achieve higher-speed ADC operation at 200-MHz clock than the conventional single-slope ADC. The simulated DNL and INL were ±0.25 LSB and ±0.43 LSB.

Published in:

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Date of Conference:

12-15 Dec. 2010