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Voltage drops are one of the most stringent problems in modern IC implementation, which is exacerbated by the ever decreasing transistor sizes and interconnect line widths. In order to find the true worst case voltage drop that a power net of a design might suffer, the designer would have to check the voltage drops that occur from the simulation of all possible input vector pairs of a design. This is a prohibitive amount of simulations for modern ICs that have hundreds of inputs. Consequently, designers face two basic challenges, fast and accurate estimation of worst case voltage-drop and accurate modeling of the power distribution network. In this paper we present a voltage-drop aware tool for power grid analysis and verification based on a statistical engine, which can estimate the true worst case voltage drops on a design with a typical confidence level of 99%. The statistical engine is based on extensions to the Extreme Value Theory (EVT) which is a pertinent field of statistics for the estimation of the unknown maximum of a related population from one (or more) of its samples. The paper shows how the statistical engine can take input from gate-level simulation of digital logic, combined with transient simulation of the power and ground network with inductance-aware (RLCK) models. Using these techniques, a designer can estimate the true worst case voltage drop on each and every contact of the power and ground distribution network of a digital design, using a relatively small amount of input vectors, thus greatly reducing the turnaround time for power integrity verification.