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This paper presents the design of a fast multi-path adiabatic CMOS driver (pr-ad). The proposed pr-ad does not uses bootstrap capacitors to minimise active area, and does not require to maintain high voltage difference across the junctions or the gates of output pull-up and output pull-down transistors. When implemented on a 65nm CMOS technology, under the large capacitive loading condition (10pF), pr-ad has a higher active area (33%), but lower energy-delay product (16%) than the reference complementary adiabatic/bootstrap circuit (cab-lwk). Also pr-ad has very small effective input capacitance in comparison with cab-lwk because the first does not need bootstrap capacitors connected with the input.