Skip to Main Content
Multiprocessors in embedded systems have a bright future with Software Defined Radio (SDR) applications where both, high performance and high adaptability are required. Framed within this statement, this paper implements the two most important SDR waveform components: FFT and Viterbi Decoding, on our designed 16 Processing Element (PE) Network on chip (NoC) based general purpose Multiprocessors System on chip (MPSoC), implemented on a single chip Xilinx Virtex-4 FPGA. We designed a parallelization strategy, by synchronizing the PEs, for each of the two algorithms and obtained a speed-up of 6 with eight PEs, for radix-2 FFT and 216 states of Viterbi Decoding. We also propose partitioning mechanism for SDR resources for PEs more than eight. The case study of our partitioning mechanism reduced execution time to 63%, thus an efficient answer to ITRS prediction.