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This work presents the design and implementation of a differential class C power amplifier (PA) in a 90 nm CMOS technology, specified to be used in a IEEE802.15.4 low power transceiver. The design is based on a PA efficiency design flow implemented in MATLAB which enables to reach very good power efficiency figures. The method is validated comparing MATLAB predicted data and post-layout SpectreRF simulated results. Post-layout simulations show a Power Amplifier Efficiency (PAE) of 46.5%, a power gain Gpow of 26dB, and an output power Pout of 1.9dBm for a 100 load, working with a supply voltage VDD = 0.65 V and a MOS DC current ID of 4.6 mA. The total area is 700 μm × 710 μm.