By Topic

Bitwidth-aware high-level synthesis for designing low-power DSP applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
G. Lhairech-Lebreton ; Université de Bretagne-Sud/Lab-STICC, France ; P. Coussy ; D. Heller ; E. Martin

Digital Signal Processing (DSP) applications are widely used from wireless communications to automotive. Their ever growing complexity and throughput still require significant parts to be implemented as dedicated hardware accelerators. A High-Level Synthesis (HLS) flow to automatically generate hardware accelerators for DSP applications is proposed in this paper. By considering bit-width information during all the synthesis process both area and power consumption are optimized. Experimental results show that the proposed approach allows to generate architectures that offer better computation accuracy for a given area and/or power consumption. Effectiveness of the approach is shown through several design experiments in the DSP domain realized on a Xilinx Virtex-5 FPGA.

Published in:

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Date of Conference:

12-15 Dec. 2010