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Leakage power is becoming the dominant power domponent in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 8T SRAM cell design considering these leakage and stability issues is proposed in this paper. Higher read static noise margin (SNM) compared to conventional 6T SRAM is achieved. The proposed SRAM is compared with a recently reported low power 8T,9T designs and the conventional 6T SRAM. Lower area compared to the 9T design and lower power consumption compared to conventional 6T, 8T and the 9T designs are reported. The adiabatic operation of this design provides further reduction in power compared to the non-adiabatic operation. The average power of the designs with process variation at 65 and 45nm processes are also reported. Power reduction of the order of 10 times (90 - 91%) is reported with the proposed design.