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In this paper we present design and optimization results of a 9T SRAM cell in a 65 nm low power technology, which previously has not been investigated for subthreshold operation. The cell is capable of both read and write operations on a supply voltage from 300mV to 1.2V. In our implementation the SRAM cell employs both high and low Vt devices for lower leakage and faster read operation. The current work focuses on operation of the cell as a single port SRAM, although extension to dual port is possible. To optimize and find trade-offs for SRAM performance in both voltage domains we use a multiobjective optimization method, where our design goals were robustness, leakage, operating speed and area. The optimization method provides an approximation of the set of all Pareto optimal designs. Based on this we may quickly select criteria for the objectives and easily optimize the rest of the parameters. Compared to recent publications the 9T cell of this paper shows promise of greatly reducing standby leakage power and good robustness while retaining a similar speed.