Process-variation tolerant design techniques for multiphase clock generation

This paper presents the design of a process-variation tolerant Delay-Locked Loop (DLL) for use in multiphase clock generation. A transistor sizing methodology to reduce delay variations with threshold voltage (V
_t
) mismatch in the Voltage Controlled Delay Line (VCDL) is proposed. Additionally, a new digital calibration scheme is proposed to further reduce the delay variations. A DLL was fabricated in a 0.6μm CMOS process and measurement results indicate reduction in the maximum mismatch in the timing error among the delay blocks from 40.1ps (3.28°) to 13.44ps (1.09°).