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Process-variation tolerant design techniques for multiphase clock generation

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3 Author(s)
Manohar Nagaraju ; University of Utah, Salt Lake City, USA ; Wei Wu ; Cameron T. Charles

This paper presents the design of a process-variation tolerant Delay-Locked Loop (DLL) for use in multiphase clock generation. A transistor sizing methodology to reduce delay variations with threshold voltage (Vt) mismatch in the Voltage Controlled Delay Line (VCDL) is proposed. Additionally, a new digital calibration scheme is proposed to further reduce the delay variations. A DLL was fabricated in a 0.6μm CMOS process and measurement results indicate reduction in the maximum mismatch in the timing error among the delay blocks from 40.1ps (3.28°) to 13.44ps (1.09°).

Published in:

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Date of Conference:

12-15 Dec. 2010