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Scan-based testing of integrated circuits produces significant switching activity during shift and capture operations, dissipating excessive power levels and, possibly, resulting in an unexpected behavior of the design. The problem is further accentuated in compression-based scan; as don't care bits are exploited to compress test patterns, additional care bits are specified in the deliverable pattern, limiting the effectiveness of x-filling techniques. In this work, we propose a low-power test method for compression-based reconfigurable scan architectures. In addition to their key objective of minimizing Test Data Volume (TDV), we illustrate how the distribution of care bits in scan chains can be manipulated, using the different encoding configurations supported by the reconfigurable scan architecture, with the objective of reducing the number of transitions during test. Hence, peak and average power of shift operation are effectively reduced. Experimental results, performed using one possible reconfigurable scan architecture as a case study, indicate that average and peak power may reduce by up to 33.8% and 26.7%, respectively, without affecting TDV and/or Test Application Time (TAT).
Design and Test Workshop (IDT), 2010 5th International
Date of Conference: 14-15 Dec. 2010