By Topic

Design and implementation of low latency network interface for network on chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Attia, B. ; Electron. & Micro-Electron. Lab., Fac. of Sci. of Monastir, Monastir, Tunisia ; Chouchene, W. ; Zitouni, A. ; Nourdin, A.
more authors

The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores. In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC. These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency. We present how we can apply decoupling between computation and communications to achieve the IP modules and interconnections to be designed independently from each other. To validate this approach, we use AMBA AHB IPs standard at the IP side and use the most three used flow control in NoC. This NI was modeled in VHDL and implemented on Xilinx Virtex5 FPGA board. Experimental results show that the proposed Network Interfaces is feasible and efficient and it is characterized by a good performance criteria's in terms of area, power, speed, latency, and Throughput.

Published in:

Design and Test Workshop (IDT), 2010 5th International

Date of Conference:

14-15 Dec. 2010