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Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm

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2 Author(s)
Alma'aitah, A. ; Dept. of Electr. & Comput. Eng., Queen''s Univ., Kingston, ON, Canada ; Abid, Z.-E.

In this paper, efficient hardware of one of the most popular encryption algorithms, the Advanced Encryption Standard (AES), is presented. A modified sub-pipelined structure is proposed targeting high speed and low power-delay product of the compact AES design with on-the-fly key expansion unit. By adding 25.8% in hardware complexity to the existing ASIC designs, the throughput is increased more than 158% with better overall power-delay product. Compared to other compact AES implementation the proposed structure can go up to 6Gbit/sec with about 13k gate count.

Published in:

Design and Test Workshop (IDT), 2010 5th International

Date of Conference:

14-15 Dec. 2010

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