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Lithography and stress variations are two dominant effects that significantly impact the functionality and performance of circuit designs at 45nm and below. Variability-aware circuit analysis methods have been introduced into the circuit design flow as one approach for implementing Design For Manufacturability (DFM) tools. These tools bridge the chip design implementation and manufacturing know-how to deliver high-value equivalent scaling advances. This paper presents an automated DFM framework that evaluates the digital design awareness of the process and physical layout effects on design performance. This study is applied on standard cell libraries and on critical paths of digital designs to monitor their differences in the physical and electrical parameters due to lithography and stress variations. An industrial FIR (Finite Inpulse Response) circuit designed in 45nm technology is used in our experiment. The results show the differences in the timing of the critical paths between the timing simulated from the standard netlist (without context awareness) and the timing simulated by using a randomly generated/actual design context aware netlist. In addition our study indicates that the variation of the timing of the critical paths differs from one industrial library to another. This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.