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Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits

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2 Author(s)
Hailong Jiao ; Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Kursun, V.

A new threshold voltage tuning methodology is explored in this paper to minimize the peak power/ground bouncing noise with smaller sleep transistors in multi-threshold CMOS (MTCMOS) circuits. Different circuit techniques with the threshold voltage tuning strategy lower the activation noise, the activation delay, and the size of the additional sleep transistors by up to 27.76%, 32.66%, and 85.71%, respectively, as compared to a previously published noise-aware MTCMOS circuit with standard zero-body-biased high threshold voltage sleep transistors in a UMC 80-nm CMOS technology.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 4 )