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1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

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4 Author(s)
Tomonori Sekiguchi ; Hitachi Europe Ltd. European R&D Centre, Maidenhead, Berkshire, United Kingdom ; Kazuo Ono ; Akira Kotabe ; Yoshimitsu Yanagawa

Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm2 assuming 4F2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 4 )