By Topic

Low power architecture design and hardware implementations of deblocking filter in H.264/AVC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hua-Chang Chung ; Dept. of Communication Engineering, National Central Univ., Jhongli, Taiwan, ROC ; Zong-Yi Chen ; Pao-Chi Chang

This paper proposes a low power deblocking filter (DF) architecture with Horizontal Edge Skip Processing Architecture (HESPA) scheme that offers an intelligent edge skip aware mechanism in filtering the horizontal edges by adopting a four-stage pipeline and adaptive hybrid filtering order to boost the speed of DF process. The proposed architecture not only reduces more than 34% logic power consumption measured in FPGA but also saves the filtering processes down to 100 clock cycles per macroblock (MB). The system throughput can easily support 1080HD video format at 30 fps with 70MHz clock frequency for low power and high definition video applications. It is implemented on 0.18μm standardized cell library, which consumes only 19.8K gates at a clock frequency of 200 MHz.

Published in:

Consumer Electronics (ICCE), 2011 IEEE International Conference on

Date of Conference:

9-12 Jan. 2011