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An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture

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4 Author(s)
Komatsu, Y. ; Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan ; Ishihara, S. ; Hariyama, M. ; Kameyama, M.

This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small area and low power of function units, while LEDR encoding for high throughput and low power of data transfer. The proposed FPGA is fabricated in the e-Shuttle 65nm CMOS process and operates at 870 MHz. Compared to the synchronous FPGA, the power consumption is reduced by 38% for the workload of 15%.

Published in:

Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific

Date of Conference:

25-28 Jan. 2011