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STARC is developing an RTL-to-GDS2 design methodology for 32nm (and 28nm) system LSIs called STARCAD-CEL. The design methodology focuses on four key areas: low power design, variation aware design and design for manufacturability as well as design productivity. This paper examines several techniques we used to solve issues the in design of challenging, leading edge devices. It also describes the effectiveness of the STARCAD-CEL design methodology when applied to the four key areas.