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Template-based memory access engine for accelerators in SoCs

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3 Author(s)
Bin Li ; Intel Labs, Hillsboro, Oregon, USA ; Zhen Fang ; Ravi Iyer

With the rapid progress in semiconductor technologies, more and more accelerators can be integrated onto a single SoC chip. In SoCs, accelerators often require deterministic data access. However, as more and more applications are running simultaneous, latency can vary significantly due to contention. To address this problem, we propose a template-based memory access engine (MAE) for accelerators in SoCs. The proposed MAE can handle several common memory access patterns observed for near-future accelerators. Our evaluation results show that the proposed MAE can significantly reduce memory access latency and jitter, thus very effective for accelerators in SoCs.

Published in:

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

Date of Conference:

25-28 Jan. 2011