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Targeting the physical gate critical dimension (CD) greatly impacts device performance. Unfortunately, advanced products within the CMOS logic 0.13 μm technology suffer from a large gate CD lot-to-lot variation, thereby causing an important device parametric characteristics variability. A novel technique is to develop a feedforward controller, which corrects for gate CD deviation by tuning the pocket implant dose. In order to enhance the controller robustness, a new scatterometry grating has been considered. The FFE-PI2 control system is simulated and then implemented in a 8" semiconductor device manufacture. Results indicate a 40% decrease in lot-to-lot variation of transistor performance.