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Tunnel field-effect transistor using InAs nanowire/Si heterojunction

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2 Author(s)
Tomioka, Katsuhiro ; Graduate School of Information Science and Technology, Research Center of Integrated Quantum Electronics (RCIQE), Hokkaido University, Sapporo 060–8628, Japan ; Fukui, Takashi

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.3558729 

We report on fabrication of tunnel field-effect transistor with III-V nanowire (NW)/Si heterojunction and surrounding-gate structure. The device fabricated by selective-area growth of an n+-InAs/undoped-InAs axial NW on a p+-Si(111) substrate showed switching behavior with an average subthreshold slope (SS) of 104 mV/dec under reverse bias condition. The switching behavior appeared under small supply voltage (Vds=50 mV). Transmission electron microscopy revealed misfit dislocation formed at the interface degraded the SS and ON-state current. Coherent growth without misfit dislocations would promise realization of steep-slope transistor with a SS of <60 mV/dec.

Published in:

Applied Physics Letters  (Volume:98 ,  Issue: 8 )

Date of Publication:

Feb 2011

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