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Simulation of yield/cost learning curves with Y4

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3 Author(s)
Nag, P.K. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Maly, W. ; Jacobs, H.J.

This paper describes a prototype of a discrete event simulator-Y4 (yield forecaster)-capable of simulating defect related yield loss and manufacturing cost as a function of time, for a multiproduct IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product, and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:10 ,  Issue: 2 )

Date of Publication:

May 1997

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