Cart (Loading....) | Create Account
Close category search window
 

Use of test structures for characterization and modeling of inter and intra-layer capacitances in a CMOS process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nouet, P. ; Lab. d''Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France ; Toulouse, Alain

In this paper, we present a global approach for inter- and intralayer capacitance characterization and modeling. Using an accurate on-chip measurement method, we have characterized realistic test patterns, i.e., test patterns consistent with capacitive couplings encountered in a layout. These reference values have allowed us to point out some limitations of current models and to propose new simple analytical models suitable for small dimension capacitive patterns. This paper emphasizes inter- and intralayer modeling

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:10 ,  Issue: 2 )

Date of Publication:

May 1997

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.