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KITE: a behavioural approach to fault-tolerance in FPGA-based systems

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5 Author(s)
Mojoli, G.A. ; Dipt. di Fisica, Milan Univ., Italy ; Salvi, D. ; Sami, M.G. ; Sechi, G.R.
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An approach to fault-tolerance in FPGAs is presented, based on multiple modular redundancy techniques that allows the designer to make full use of conventional CAD tools, avoiding low-level mapping problems and choosing-for the functions to which the approach is applied-the level of granularity best suited to the individual application. The single-fault model is considered insufficient, in view of experience gathered: thus the technique adopted allows one to detect up to two initial faults or to recover from up to two faults appearing sequentially in time. The structure proposed for the arbiter subsystem allows one to detect a large number of faults appearing in the arbiter as well; probability of faults appearing in the hard-core section is evaluated

Published in:

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Date of Conference:

6-8 Nov 1996