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Optimising high-level synthesis for self-checking arithmetic circuits

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3 Author(s)
Antola, A. ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; Piuri, V. ; Sami, M.

Introduction of self-checking capacity in arithmetic systems since the initial steps of high-level synthesis is taken into account, as an alternative to conventional solutions that adopt ad-hoc coding or comparable techniques after the register-level architecture has been fully defined. A technique based on initial partitioning of the Data Flow Graph into detectable subgraphs is proposed, by which all single errors appearing within one subgraph are detected; an algorithm leading to optimize resource sharing (allocation and binding of both functional units and registers) while keeping minimum latency and optimum number of checkers is discussed

Published in:

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Date of Conference:

6-8 Nov 1996