By Topic

Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Rakheja, S. ; Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA ; Naeemi, A.

Power dissipation in charge-based technology is the biggest roadblock toward miniaturizing circuits. Quantum-mechanical tunneling and subthreshold leakage current will ultimately limit scaling of silicon field-effect transistors. To continue Moore's law scaling, it is imperative that devices working with a state variable other than electron charge are sought for. Examples of alternate state variables include electron spins, pseudo-spins in graphene, direct and indirect excitons, plasmons, and phonons. At the same time, interconnection aspects of devices utilizing novel state variables must be considered early on. This paper provides a framework to quantify energy dissipation in interconnects for novel state variables. Models for energy per bit are then used along with previously derived models for delay of interconnects for novel state variables to compare performance and energy dissipation of novel interconnects with complementary metal-oxide-semiconductor (CMOS) interconnects. Comparison results provide important insights into material, device, and circuit implications of post-CMOS technologies.

Published in:

Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 5 )