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Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

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4 Author(s)
Nikolos, D. ; Dept. of Comput. Eng. & Inf., Patras Univ., Greece ; Verges, H.T. ; Vazaios, A. ; Voulgaris, S.

In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace driven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the minimum performance degradation

Published in:

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Date of Conference:

6-8 Nov 1996