Referenced Items are not available for this document.
In this paper a yield model for single chip VLSI processors with two level on-chip caches is derived. Using this model and trace driven simulations the distribution of the faulty cache blocks into the first and second level caches can be determined so as to achieve a significant yield enhancement with the minimum performance degradation
Published in:
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Date of Conference: 6-8 Nov 1996
- Page(s):
- 53 - 57
- Meeting Date :
- 06 Nov 1996-08 Nov 1996
- ISSN :
- 1063-6722
- Print ISBN:
- 0-8186-7545-4
- INSPEC Accession Number:
- 5527024
- Conference Location :
- Boston, MA
- Digital Object Identifier :
- 10.1109/DFTVS.1996.571989
- Product Type:
- Conference Publications
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