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Pulsed-Latch Circuits: A New Dimension in ASIC Design

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2 Author(s)
Youngsoo Shin ; KAIST, Daejeon, South Korea ; Seungwhun Paik

Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher performance and lower power consumption within a conventional ASIC design environment. This article identifies a design methodology and tools for pulsed-latch ASICs to complement this environment. The authors review potential solutions and provide quantitative results to assess the effectiveness of pulsed-latch circuits.

Published in:

Design & Test of Computers, IEEE  (Volume:28 ,  Issue: 6 )