Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL

Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.