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Vertical Si-Nanowire n -Type Tunneling FETs With Low Subthreshold Swing ( \leq \hbox {50} \hbox {mV/decade} ) at Room Temperature

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5 Author(s)
Ramanathan Gandhi ; Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR) , Singapore ; Zhixian Chen ; Navab Singh ; Kaustav Banerjee
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This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.

Published in:

IEEE Electron Device Letters  (Volume:32 ,  Issue: 4 )