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A low power dual-channel asynchronous successive approximation register (ASAR) analog-to-digital converter (ADC) is presented. A metastable-then-set (MTS) algorithm is proposed with the aim of eliminating unnecessary decision operations in ASAR and its effects on power consumption and performance have been measured. The proposed flag synchronization technique minimizes the crosstalk between two asynchronous ADCs. A prototype ADC was implemented in 0.13-μm CMOS technology and operated under a 1.2 V supply. At a sampling rate of 17.5 MS/s, the ADC achieves a peak signal-to-noise and distortion ratio of 51.3 dB at 1.73 MHz input frequency. The measured total power dissipation of a single channel ADC is 570 μW and the figure of merit is 103 fJ/step.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20 , Issue: 4 )
Date of Publication: April 2012