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4×2Gbps Source-Synchronous Transmitter in 45nm CMOS

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3 Author(s)
Anant S. Kamath ; Analog Interfaces & Sub-Syst., Texas Instrum. India Pvt. Ltd., Bangalore, India ; Vikas Sinha ; Sujoy Chakravarty

A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.

Published in:

2011 24th Internatioal Conference on VLSI Design

Date of Conference:

2-7 Jan. 2011