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Scale the Supply, Reduce the Area and Use Digital Gates: We focus on three themes aimed at designing analog and RF interface circuits in digital nanoscale CMOS processes. Design techniques for analog and RF circuits operating well below IV can keep them compatible with future low power SOCs. Scaling the size of RF circuits and reclaiming the space under inductors is necessary to reduce area and cost. The abundance of digital gates makes it possible to use digitally assisted self-calibration for RF front ends to improve linearity and interference robustness and even simplify design.