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Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

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6 Author(s)
Chun-Jung Su ; Nano Facility Center, Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tzu-I Tsai ; Yu-Ling Liou ; Lin, Zer-Ming
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In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.

Published in:

Electron Device Letters, IEEE  (Volume:32 ,  Issue: 4 )

Date of Publication:

April 2011

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