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This paper presents a 0.6-V voltage doubler and a 0.6-V clocked comparator in 65 nm CMOS. For the multi-phase sampling application, such as charge-domain correlator for impulse UWB receivers or analog-to-digital converter, the proposed voltage doubler can reduce the power consumption and the chip area by half compared to the conventional one. The non-overlapping complementary clock generator used in the conventional voltage doubler can be eliminated by simply swapping the input clock order in the voltage doubler. The proposed 0.6-V clocked comparator can operate at 100-MHz clock with the proposed voltage booster.
Date of Conference: 8-10 Nov. 2010