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A 120-GHz transmitter and receiver chipset with 9-Gbps data rate using 65-nm CMOS technology

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5 Author(s)
Fujimoto, R. ; ELP R&D Dept., Semicond. Technol. Acad. Res. Center (STARC), Tokyo, Japan ; Motoyoshi, M. ; Yodprasit, U. ; Takano, K.
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The design and measured results of a 120-GHz transmitter and receiver chipset are described in this paper. A simple amplitude shift keying (ASK) is adopted for this chipset. The proposed transmitter and receiver are fabricated using 65-nm CMOS technology. The current consumptions are 19.2 mA for the transmitter and 48.2 mA for the receiver. A 9-Gbps PRBS is successfully transferred from the transmitter to the receiver with the bit error rate less than 10-9.

Published in:

Solid State Circuits Conference (A-SSCC), 2010 IEEE Asian

Date of Conference:

8-10 Nov. 2010