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A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links

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2 Author(s)
Sanquan Song ; Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA ; Stojanovic, V.

Fractionally spaced linear receive equalization (FSE) is shown in this work as an effective method to perform joint equalization and phase-synchronization in mesochronous high-speed links. Given an arbitrary receive sampling phase, a modified sign-sign least mean squares (M-SSLMS) adaptive algorithm is developed to tune the FSE tap weights to mitigate the inter-symbol interference (ISI), avoiding the divergence issue in the standard sign-sign least mean squares (SSLMS) algorithm. To achieve the desired linearity with good energy efficiency and large input dynamic range, an FSE is implemented using a voltage-time conversion technique by inverter-based threshold detectors with auto-zeroing function. The two-tap quad-rate FSE receiver with one-tap DFE is fabricated in 90 nm bulk CMOS technology, occupying 0.03 mm 2 active area. With a 1.2 V supply, it achieves a 6.25 Gb/s rate, 3.6 mW/Gb/s efficiency and over 4 bits of linearity.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 5 )

Date of Publication:

May 2011

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