Skip to Main Content
Fast design space exploration of complex nano-CMOS mixed-signal circuits is an important problem. In this paper, a design process flow that uses metamodels is introduced. In this flow the most important task is the sampling of the design space. In this paper, different sampling techniques for producing an accurate metamodel are investigated to minimize the number of samples required by using a nano-CMOS ring oscillator (RO) as an example. Through SPICE simulations, it is shown that the parasitics have a drastic effect on performance metrics, such as the frequency of oscillation. Alternative sampling techniques, both random, such as Monte Carlo (MC), and uniform, such as Latin Hypercube Sampling (LHS), and Design of Experiments (DOE), are considered as and compared for speed and accuracy. Due to the time constraints of the circuit design process, this paper can be used as a guideline for which sampling technique will produce the most accurate result to minimize the design time. All a experimental results are presented for a 45 nm technology.