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In this paper, we propose a novel methodology to automate the transistor-level sizing of OpAmps. Given the net list and the specifications of the OpAmp, our methodology automatically produces a set of monomial design equations that can be solved using geometric programming. The use of monomial models eliminates the overhead of generating elaborate posynomial design equations. The proposed approach is based on the use of circuit heuristics to generate a first order design model, which is then refined by adopting a localized simulation scheme. This approach produces a design that has the accuracy of the BSIM models used for simulation and the advantage of a quick design time. The results of a two stage OpAmp designed in TSMC 0.25μ technology prove the efficacy of our approach.