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History and Trends in Analog Circuit Challenges at the System Level

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1 Author(s)
Gray, R. ; Converged Core Dev. Organ., Intel Corp., Hillsboro, CA, USA

In contemporary systems much of the system is embodied in the silicon components. A good example is Intel's Huron River mobile platform, comprising the Sandy Bridge microprocessor and Cougar Point PCH (Platform Controller Hub). The microprocessor component contains up to four CPU cores, an integrated memory controller supporting dual-channel DDR3, PCIe Generation 2, and integrated graphics. The SATA, USB, and display interfaces reside in the PCH component. Both the microprocessor and PCH components represent significant complexity, not only from a logic point of view, but also from an analog circuit point of view. Contemporary platform signaling speeds include up to 1600 Mb/s single-ended DDR3 and 5 Gb/s differential PCIe Gen2. The typical circuit board material in systems has limitations that require analog complexity to overcome the limits. The risk for post-Si bugs in these circuits is proportional to the circuit complexity. Complicating this is the need to conserve both power and silicon die area: both challenging to the analog circuit designer, and both adding to the overall design complexity. One other factor affecting analog circuitry is in the mixed signal domain, seen primarily in the timing convergence domain. Interfaces - whether single-ended memory channels or differential PCIe channels - are governed by strict clocking and timing budgets. As the signaling speed increases, the clock and timing budgets continue to shrink. This also fuels the risk of circuit bugs. This talk will examine the history and trends of analog and circuit issues that have evolved as system-level integration has been increasing.

Published in:

Electronic System Design (ISED), 2010 International Symposium on

Date of Conference:

20-22 Dec. 2010