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Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

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2 Author(s)
M. Kakumu ; Toshiba Corp., Kawasaki, Japan ; M. Kinugawa

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1EcLeff, where Ec is the critical electric field necessary to cause carrier velocity saturation and Leff is the effective channel length, is introduced. Experimental results confirmed that 1.1EcLeff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 μm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1EcLeff can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-μm channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1EcLeff

Published in:

IEEE Transactions on Electron Devices  (Volume:37 ,  Issue: 8 )